Basic Properties

CircuitNet-N28

All features under the directories routability_features and IR_drop_features are tile-based. Most information in layout is mapped into tiles with a size of $2.25\mu m \times 2.25\mu m$. Moreover, layouts are around $450\mu m \times 450\mu m$, resulting in feature maps of around $300 \times 300$ tiles. In summary, most of the feature maps are 2-dimension numpy array [w, h] unless otherwise indicated. Their detailed calculations are described in the following sections.

Note that the features need to be preprocessed for training, including resizing and normalization. We provide script of our customized preprocessing method used in our experiment, but there is more than one way to complete preprocessing.

10242 samples are generated for feature extraction from 6 original RTL designs with variations in synthesis and physical design as shown in table below.

The naming convention for extracted feature maps is defined as: {Design name}-{#Macros}-c{Clock}-u{Utilizations}-m{Macro placement}-p{Power mesh setting}-f{filler insertion}

Here is an example: RISCY-a-1-c2-u0.7-m1-p1-f0

CircuitNet-N14

10345 samples are generated for feature extraction from 8 original RTL designs with variations in synthesis and physical design as shown in table below.

The naming convention for extracted feature maps is defined as: {Design name}_freq_{#freq}_mp_{Macro palcement}_fpu_{Utilizations}_fpa_{Aspect Ratio}_p_{Power mesh setting}_fi_{Filler insertion stage}

Here is an example: RISCY_freq_50_mp_1_fpu_60_fpa_1.0_p_7_fi_ar