# Basic Properties

All features are tile-based. Most information in layout is mapped into tiles with a size of 1.5$\mu$m$\times$1.5$\mu$m. Moreover, layouts are around 450$\mu$m$\times$450$\mu$m, resulting in feature maps of around 300$\times$300 tiles. In summary, most of the feature maps are 2-dimension numpy array [w, h] unless otherwise indicated. Their detailed calculations are described in the following sections.

Note that the features need to be preprocessed for training, including resizing and normalization. We provide script of our customized preprocessing method used in our experiment, but there is more than one way to complete preprocessing.

# Naming Conventions

10242 samples are generated for feature extraction from 6 original RTL designs with variations in synthesis and physical design as shown in table below.

Design Synthesis Variations Physical Design Variations
#Macros Frequency
(MHz)
Utilizations
(%)
#Macro
Placement
#Power Mesh
Setting
Filler Insertion
RISCY-a

3/4/5

50/200/500

70/75/80/85/90

3

8

After Placement
/After Routing
RISCY-FPU-a
zero-riscy-a
RISCY-b

13/14/15
RISCY-FPU-b
zero-riscy-b

The naming convention for extracted feature maps is defined as: {Design name}-{#Macros}-c{Clock}-u{Utilizations}-m{Macro placement}-p{Power mesh setting}-f{filler insertion}

Here is an example: RISCY-a-1-c2-u0.7-m1-p1-f0

Comparison table
Design name 6 RTL designs
#Macros 3/4/5 or 13/14/15 1/2/3
Clock Frequency 500/200/50 MHz Clock period 2/5/20 ns
Utilizations 70/75/80/85/90% 0.7/0.75/0.8/0.85/0.9
Macro placement 3 1/2/3
Power mesh setting 8 1/2/3/4/5/6/7/8
filler insertion After placement/After routing 1/0