Introduction

CircuitNet is an open-source dataset dedicated to machine learning (ML) applications in electronic design automation (EDA). We have collected more than 20K samples from versatile runs of commercial design tools based on open-source designs with various features for multiple ML for EDA applications.

Available Datasets

We currently maintain three variations of datasets: CircuitNet-N28, CircuitNet-N14, and CircuitNet-ISPD15. All datasets are collected from commercial design tools, but differ in underlying designs and technology nodes.

CircuitNet-N28

• Design Basis: RISC-V designs
• Technology: 28nm planar technology
• Status: Most comprehensive support for all tasks
• Applications: Full support for all prediction tasks

CircuitNet-N14

• Design Basis: Multiple designs including RISC-V, GPU, and ML accelerator
• Technology: 14nm FinFET technology
• Current Support: Congestion prediction, IR drop prediction, Net delay prediction
• Future Plans: DRC prediction support coming soon

CircuitNet-ISPD15

• Design Basis: ISPD2015 contest benchmark
• Current Support: Congestion prediction
• Future Plans: DRC prediction support coming soon

Feature Support Matrix

The following table shows the feature support status for each dataset:

Legend: ✅ = Supported, ❌ = Not Supported, N/A = Not Applicable

Directory Structure

All datasets follow a similar directory structure to enable flexible feature combinations and custom applications.

Feature Organization

📁 .
├─ 📁 routability_features
│  ├─ 📄 cell_density
│  ├─ 📁 congestion
│  │  ├─ 📁 congestion_early_global_routing
│  │  │  ├─ 📁 overflow_based
│  │  │  │  ├─ 📄 congestion_eGR_horizontal_overflow
│  │  │  │  └─ 📄 congestion_eGR_vertical_overflow
│  │  │  └─ 📁 utilization_based
│  │  │     ├─ 📄 congestion_eGR_horizontal_util
│  │  │     └─ 📄 congestion_eGR_vertical_util
│  │  └─ 📁 congestion_global_routing
│  │     ├─ 📁 overflow_based
│  │     │  ├─ 📄 congestion_GR_horizontal_overflow
│  │     │  └─ 📄 congestion_GR_vertical_overflow
│  │     └─ 📁 utilization_based
│  │        ├─ 📄 congestion_GR_horizontal_util
│  │        └─ 📄 congestion_GR_vertical_util
│  ├─ 📁 DRC
│  │  ├─ 📄 DRC_all
│  │  └─ 📄 DRC_seperated
│  ├─ 📄 macro_region
│  └─ 📁 RUDY
│     ├─ 📄 RUDY
│     ├─ 📄 RUDY_long
│     ├─ 📄 RUDY_short
│     ├─ 📄 RUDY_pin
│     └─ 📄 RUDY_pin_long
└─ 📁 IR_drop_features
   ├─ 📄 power_i
   ├─ 📄 power_s
   ├─ 📄 power_sca
   ├─ 📄 power_all
   ├─ 📄 power_t
   └─ 📄 IR_drop

Feature Usage

• Features are organized in separate directories to enable:

  • Custom feature combinations
  • Flexible preprocessing methods
  • Task-specific feature selection

• Provided scripts can help you:

  • Preprocess the raw features
  • Combine features for specific tasks
  • Prepare training and testing datasets

• You are encouraged to:

  • Implement your own preprocessing methods
  • Experiment with different feature combinations
  • Develop novel feature engineering approaches